An investigation into the power-performance trade-off in memristor-augmented sense amplifiers for nanoscale SRAM

Abstract

As technology ramps up to high nodes, SRAM sense amplifiers struggle suffer from increasing static power. The paper proposes memristors as non-volatile, tunable loads in cross-coupled differential sense amplifiers as a remedy. Simulation in a 45 nm node reveals 69.2 % leakage power reduction, making the solution appealing for low-power usage. The static power reduction comes at the expense of 12 % and 52.5 % elevated dynamic power and output noise at 1.2 V respectively. Hence, the memristor-based design is best suited for low-duty-cycle, leakage-critical applications and not as generalised CMOS replacement, dictating application-specific powerperformance co-design.