Browsing Сериальные издания by Author "Prihozhy, A. A."

Now showing items 1-6 of 6

    • Influence of shortest path algorithms on energy consumption of multi-core processors 

      Prihozhy, A. A.; Karasik, O. N. (БНТУ, 2023)
      Modern multi-core processors, operating systems and applied software are being designed towards energy efficiency, which significantly reduces energy consumption. Energy efficiency of software depends on algorithms it implements, and, on the way, it exploits hardware resources. In the paper, we consider sequential and parallel implementations of four algorithms of shortest paths ...
      2023-10-13

    • New blocked all-pairs shortest paths algorithms operating on blocks of unequal sizes 

      Prihozhy, A. A.; Karasik, O. N. (БНТУ, 2023)
      BelarusIn real-world networks, many problems imply finding the All-Pairs Shortest Paths (APSP) and their distances in a graph. Solving the large-scale APSP problem on modern muti-processor (multi-core) systems is the key for various application domains. The computational cost of solving the problem is high, therefore in many cases approximate solutions are considered as acceptable. ...
      2024-01-19

    • Optimization of data allocation in hierarchical memory for blocked shortest paths algorithms 

      Prihozhy, A. A. (БНТУ, 2021)
      This paper is devoted to the reduction of data transfer between the main memory and direct mapped cache for blocked shortest paths algorithms (BSPA), which represent data by a D[M×M] matrix of blocks. For large graphs, the cache size S = δ×M2, δ < 1 is smaller than the matrix size. The cache assigns a group of main memory blocks to a single cache block. BSPA performs multiple ...
      2021-10-01

    • Simulation of direct mapped, k-way and fully associative cache on all pairs shortest paths algorithms 

      Prihozhy, A. A. (БНТУ, 2019)
      Caches are intermediate level between fast CPU and slow main memory. It aims to store copies of frequently used data and to reduce the access time to the main memory. Caches are capable of exploiting temporal and spatial localities during program execution. When the processor accesses memory, the cache behavior depends on if the data is in cache: a cache hit occurs if it is, and, ...
      2020-01-09

    • Synthesis of parallel adders from if-decision diagrams 

      Prihozhy, A. A. (БНТУ, 2020)
      Addition is one of the timing critical operations in most of modern processing units. For decades, extensive research has been done devoted to designing higher speed and less complex adder architectures, and to developing advanced adder implementation technologies. Decision diagrams are a promising approach to the efficient many-bit adder design. Since traditional binary decision ...
      2020-08-19

    • Tuning block-parallel all-pairs shortest path algorithm for efficient multi-core implementation 

      Karasik, O. N.; Prihozhy, A. A. (БНТУ, 2022)
      Finding shortest paths in a weighted graph is one of the key problems in computer-science, which has numerous practical applications in multiple domains. This paper analyzes the parallel blocked all-pairs shortest path algorithm at the aim of evaluating the influence of the multi-core system and its hierarchical cache memory on the parameters of algorithm implementation depending ...
      2022-12-07